FIG. 1 is a schematic diagram showing connections between memory cells, word lines, and plate lines in a conventional FeRAM. FIG. 2 is a schematic diagram showing connections between the memory cells and bit lines in the conventional FeRAM.
As shown in FIG. 1, a pair of row selection lines, consisting of a word line W and a plate line P, are connected to a group of memory cells in the row direction (henceforth, a memory-cell row) in a one-to-one relationship in the conventional FeRAM. Namely, in FIG. 1, a pair of first-row selection lines W1 and P1 are connected to memory cells 11, 12, 13, . . . in the first row. A pair of second-row selection lines W2 and P2 are connected to memory cells 21, 22, 23, . . . in the second row. A pair of third-row selection lines W3 and P3 are connected to memory cells 31, 32, 33, . . . in the third row.
As shown in FIG. 2, a pair of column selection lines, consisting of a pair of bit lines B and B, are connected to a group of memory cells in the column direction (henceforth, a memory-cell column) in a one-to-one relationship in the conventional FeRAM. Namely, in FIG. 2, a pair of first-column selection lines B11 and B12 are connected to the memory cells 11, 21, . . . in the first column. A pair of second-column selection lines B21 and B22 are connected to the memory cells 12, 22, . . . in the second column. A pair of third-column selection lines B31 and B32 are connected to the memory cells 13, 23, . . . in the third column. A pair of fourth-column selection lines B41 and B42 are connected to the memory cells 14, 24, . . . in the fourth column.
Let us consider a case of the FeRAM in which memory cells are formed with two transistors and two ferroelectric elements (ferroelectric capacitors). In such a FeRAM, the memory cells are structured as shown in FIG. 3. Namely, one electrode of each of the two ferroelectric elements C1 and C2 in each of the memory cells 11, 12, . . . , 21, 22, . . . are connected to different transistors Q1 and Q2. Whereas the other electrodes of the ferroelectric elements C1 and C2 are connected to the plate lines P1 and P2, respectively.
When the FeRAM is to be fabricated, it is generally required to write cipher or the like in a memory cell that consists of ferroelectric elements in the stage of wafer process of the fabrication process. That is because it is not preferable from the viewpoint of data security that the write operation is performed after the completed FeRAM-chip package has been mounted on a circuit board.
It has been known that external factors such as heat or hydrogen cause degradation in the characteristics of the ferroelectric element. Accordingly, even if the cipher or the like are written in the ferroelectric memory cell in the wafer process, memory information may be lost due to degradation in the characteristics of the ferroelectric memory cell. More specifically, this degradation is caused by the fact that the ferroelectric element is affected by heat or when exposed to hydrogen during the fabrication process after the write operation has been performed. The loss of stored information is a great disadvantage from the viewpoint of reliability.
During the conventional fabrication process as explained above, however, the external factors such as heat or hydrogen need to be removed as much as possible. Therefore, the fabrication process is restricted by this requirement. Further, some facilities to eliminate the influence of heat or hydrogen on the process are needed, which is different from the manufacturing facilities of an ordinary DRAM or the like. Thus, the manufacturing cost increases, which results in the costly FeRAM package.